In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically are synchronized to external operations.
Internal clock signals that are synchronized with the external clock signal are generated in order to execute internal operations in synchronicity with the external operations. To synchronize external and internal clock signals in modern synchronous memory devices include clock signal generators that generate internal clock signals in response to external clock signals. A number of different approaches have been considered and utilized to implement clock signal generators, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art.
A DLL is a feedback circuit that operates to feed back a phase difference-related signal to control an adjustable delay line, until the timing of a first clock signal, for example, the system clock, is advanced or delayed such that its rising edge is coincident (or “locked”) with the rising edge of a second clock signal, for example, the memory internal clock. The adjustable delay line typically includes a coarse adjustable portion and a fine adjustable portion. The fine adjustable portion provides higher adjustment resolution to synchronize the clock signals. Typically, the fine adjustable portion is implemented as a series of fine delay stages that can be activated or deactivated as necessary to provide the required fine delay for synchronization. Another example of a fine adjustable portion is provided by a phase mixer, for example, as described in U.S. Pat. No. 7,417,478 to Kim et al.
Phase mixers are used for their ability to do very high resolution digital-to-time conversion. For example, for a two-signal input phase mixer, an output signal is generated from two input signals that are out of phase. The resulting output signal has a phase relative to the phase difference of the two input signals. A weakness of a phase mixer, however, is that non-linearity of the phase mixer response increases with phase difference of the input signals. That is, the greater the phase difference of the input signals, the greater the non-linear response of the phase mixer. As a result, controlling a phase mixer over a broad range of phase differences increases complexity of control circuitry and its operation to accommodate the increasing non-linear response.